Simulation and characterization of large integrated circuits (ICs) induces a heavy burden on the memory usage of simulation engines. Consequently, process computation in large IC simulation is scheduled around the availability of memory resources, often slowing down the simulation completion. In many instances, this memory bottleneck is a driving cost of the IC simulation. This limitation becomes more acute in applications where the IC design includes a memory device (e.g., SRAM and the like), where large, mostly repetitive circuit blocks are simulated under multiple conditions and parameters. Typically, multiple circuit blocks in SRAM simulations are treated separately, introducing redundancies in memory usage, ultimately slowing down the simulation pipeline. A slowed simulation reduces turnaround time for IC design, unnecessarily extending the time to market for appliances and devices.
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